This chapter documents the Memory Controller MCHBAR registers.
Base address of these registers are defined in the MCHBAR_​0_​0_​0_​PCI register in Bus 0, Device 0, Function 0.
The processor has 2 memory controllers. Each memory controller has 2 channels. Each channel can drive up to 2 sub channels depending on the memory type:
• LPDDR4x\LPDDR5:
— 2 Memory controllers
— 2 Channels per memory controller (total 4)
— 2 sub channels per channel (total 8)
• DDR4:
— 2 Memory controllers
— 1 Channel per memory controller (total 2)
— No sub channels
• DDR5:
— 2 Memory controllers
— 2 Channels per memory controller (total 4)
— No sub channels
The MCHBAR exposes 3 sets of memory controller registers per controller for channel 0, channel 1 as well as broadcast.
• Memory Controller 0 (MC0)
— Channel 0 offset range: E000h-E7FFh
— Channel 1 offset range: E800h-EFFFh
— Broadcast offset range: F000h-F7FFh
— Shared registers: D800h-DFFFh
• Memory Controller 1 (MC1)
— Channel 0 offset range: 1E000h-1E7FFh
— Channel 1 offset range: 1E800h-1EFFFh
— Broadcast offset range: 1F000h-1F7FFh
— Shared registers: 1D800h-1DFFFh
Memory Controller Broadcast register behavior is to write to all channels of the same memory controller and read from channel 0.
Note: For brevity, only Channel 0 and the shared registers of MC0 are documented:
• MC0 Channel 1: MC0 Channel 0 + 0800h
• MC0 Broadcast: MC0 Channel 0 + 1000h
• MC1 Channel 0: MC0 Channel 0 + 10000h
• MC1 Channel 1: MC0 Channel 0 + 10800h
• MC1 Broadcast: MC0 Channel 0 + 11000h
• MC1 Shared: MC0 Shared + 10000h