12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers Registers
This chapter documents the PXPEPBAR registers.
Base address of these registers are defined in the PXPEPBAR_0_0_0_PCI register in Bus 0, Device 0, Function 0.
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
0h | 4 | 00000000h | |
4h | 4 | 00000000h | |
8h | 4 | 00000000h | |
Ch | 4 | 00000000h | |
10h | 4 | Egress Port Virtual Channel 0 Resource Capability (EPVC0RCAP) | 00000000h |
14h | 4 | 00000000h | |
1Ah | 2 | 0000h | |
1Ch | 4 | Egress Port Virtual Channel 1 Resource Capability (EPVC1RCAP) | 00000000h |
20h | 4 | 00000000h | |
26h | 2 | 0000h | |
40h | 4 | 00000000h | |
44h | 4 | 00000000h | |
50h | 4 | 00000000h | |
58h | 4 | Egress Port Link Another Root Complex Declaration 1 (EPLE1A) | 00000000h |
5Ch | 4 | 00000000h | |
60h | 4 | 00000000h | |
68h | 4 | Egress Port Link Another Root Complex Declaration 2 (EPLE2A) | 00000000h |
6Ch | 4 | 00000000h | |
70h | 4 | 00000000h | |
78h | 4 | Egress Port Link Another Root Complex Declaration 3 (EPLE3A) | 00000000h |
7Ch | 4 | 00000000h | |
80h | 4 | 00000000h | |
88h | 4 | Egress Port Link Another Root Complex Declaration 4 (EPLE4A) | 00000000h |
8Ch | 4 | 00000000h | |
90h | 4 | 00000000h | |
98h | 4 | Egress Port Link Another Root Complex Declaration 5 (EPLE5A) | 00000000h |
9Ch | 4 | 00000000h | |
A0h | 4 | 00000000h |