12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
D10:F0 Platform Monitoring Technology (PMT) Registers Registers
This chapter documents the registers in Bus 0, Device 10, Function 0.
Platform Monitoring Technology (PMT) Registers.
The device has an SRAM that has the following data:
• Telemetry: records a snapshot of the system state.
• CrashLog: records the system information during a crash/hang.
Note: While SSRAM can contain Crashlog data, the Crashlog data is not accessible/retrievable using the PMT device interface. It could be provided by the BIOS through other mechanisms.
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
0h | 4 | 00000000h | |
4h | 4 | 00000000h | |
8h | 4 | 00000000h | |
Ch | 4 | Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE) | 00000000h |
10h | 8 | 0000000000000000h | |
2Ch | 4 | Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID) | 00000000h |
34h | 4 | 00000000h | |
3Ch | 4 | 00000000h | |
70h | 4 | 00000000h | |
74h | 4 | 00000000h | |
78h | 4 | 00000000h | |
D0h | 4 | 00000000h | |
D4h | 4 | 00000000h | |
100h | 4 | 00000000h | |
104h | 4 | 00000000h | |
108h | 4 | 00000000h | |
10Ch | 4 | 00000000h | |
110h | 4 | 00000000h | |
114h | 4 | 00000000h | |
118h | 4 | 00000000h | |
11Ch | 4 | 00000000h | |
120h | 4 | 00000000h | |
124h | 4 | 00000000h | |
128h | 4 | 00000000h | |
12Ch | 4 | 00000000h |