31:29

0h

RO

Reserved

28

0x0

RO

Function Level Reset Capable (FLRC)

Not supported in Root Ports

27:26

0x0

RO

Captured Slot Power Limit Scale (CSPS)

Not supported.

25:18

0x0

RO

Captured Slot Power Limit Value (CSPV)

Not supported.

17:16

0h

RO

Reserved

15

0x1

RO

Role Based Error Reporting (RBER)

Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec.

14:12

0h

RO

Reserved

11:9

0x0

RO

Endpoint L1 Acceptable Latency (E1AL)

Reserved for root ports.

8:6

0x0

RO

Endpoint L0s Acceptable Latency (E0AL)

Reserved for Root port.

5

0x0

RW/O

Extended Tag Field Supported (ETFS)

The Root Port never needs to initiate a transaction as a Requester with the Extended Tag bits being set. This bit does not affect the root port's ability to forward requests as a bridge as the root port always supports forwarding requests with extended tags.

4:3

0x0

RO

Phantom Functions Supported (PFS)

No phantom functions supported

2:0

0x1

RW/L

Max Payload Size Supported (MPS)

BIOS should write to this field during system initialization.
Max Payload Size of up to 256B is supported. Programming this field to any values other than 128B or 256B max payload size will result in aliasing to 128B max payload size.
0: 128 bytes max payload size.
1: 256 bytes max payload size.
2: 512 bytes max payload size.
3: 1024 bytes max payload size.
4: 2048 bytes max payload size.
5: 4096 bytes max payload size.
6: Reserved.
7: Reserved.
This field applies only to the PCIe link interface.