12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Device Capabilities (DEVICECAP_0_2_0_PCI) – Offset 74
PCI Express Device Capabilities
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RO | Reserved |
28 | 0x1 | RO | Functional Level Reset Capability (FLRCAP) Hardwired to 1b to indicate the Function supports the optional Function Level Reset mechanism. |
27:26 | 0x0 | RO | Captured Slot Power Limit Scale (PWR_LIM_SCALE) Not applicable for a Root Complex Integrated Endpoint with no Link or Slot. Hardwired to 00b |
25:18 | 0x0 | RO | Captured Slot Power Limit Value (CSPLS) Not applicable for a Root Complex Integrated Endpoint with no Link or Slot. Hardwired to 00h |
17:16 | 0h | RO | Reserved |
15 | 0x1 | RO | Role-Based Error Reporting (RBER) When Set, this bit indicates that the Function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1.Hardwired to 1b as this bit must be Set by all Functions conforming to the ECN, PCI Express Base Specification, Revision 1.1, or subsequent PCI Express Base Specification revisions. |
14:12 | 0h | RO | Reserved |
11:9 | 0x0 | RO | Endpoint L1 Acceptable Latency (EPL1AL) This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L1 state to the L0 state.This does not apply to the integrated graphics device, so it is hardwired to 000b (Maximum of 1 us). |
8:6 | 0x0 | RO | Endpoint L0S Acceptable Latency (EPL0AL) This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L0s state to the L0 state.This does not apply to the integrated graphics device, so it is hardwired to 000b (Maximum of 64 ns). |
5 | 0x0 | RO | Extended Tag Field Supported (ETFS) This bit indicates the maximum supported size of the Tag field as a Requester.This does not apply to the integrated graphics device, so it is hardwired to 0b (5-bit Tag field supported). |
4:3 | 0x0 | RO | Phantom Functions Supported (PFS) This field indicates the support for use of unclaimed Function Numbers to extend the number of outstanding transactions for PCIe devices.This does not apply to the integrated graphics device, so it is hardwired to 00b to indicate no Function Number bits are used for Phantom Functions. |
2:0 | 0x0 | RO | Max Payload Size Supported (MPSS) This field indicates the maximum payload size that the Function can support for TLPs.Hardwired to 000b to represents 128 bytes, the minimum allowed value. |