12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Device Control (DCTL) – Offset 48
Device Control
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RO | Reserved |
14:12 | 0x0 | RO | Max Read Request Size (MRRS) Hardwired to 0. |
11 | 0x0 | RO | Enable No Snoop (ENS) Not supported. The root port will never issue non-snoop requests. |
10 | 0x0 | RW/P | Aux Power PM Enable (APME) Must be RW for OS testing. The OS will set this bit to 1 if the device connected has detected aux power. It has no effect on the root port otherwise. |
9 | 0x0 | RO | Phantom Functions Enable (PFE) Not supported |
8 | 0x0 | RO | Extended Tag Field Enable (ETFE) Not supported |
7:5 | 0x1 | RW | Max Payload Size (MPS) The root port supports up to 256B max payload. |
4 | 0x0 | RO | Enable Relaxed Ordering (ERO) Not supported |
3 | 0x0 | RW | Unsupported Request Reporting Enable (URE) When set, allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). |
2 | 0x0 | RW | Fatal Error Reporting Enable (FEE) Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |
1 | 0x0 | RW | Non-Fatal Error Reporting Enable (NFE) When set, enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |
0 | 0x0 | RW | Correctable Error Reporting Enable (CEE) When set, enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |