12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) – Offset 59C8
MDID override register to be used by OS or software for debug purposes.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RO | Reserved |
30 | 0x0 | RW | Force MDID Override (FORCE_MDID_OVERRIDE) When this bit is set, and bit 1 (the valid bit) is set, the value specified in this field will be used for MDID purposes. If this bit is clear, and bit 1 (the valid bit) is set, this value should be consumed along with the other MDID registers to determine which value is expiring next and reporting that value. |
29 | 0x0 | RW | Disable MDID Evaluation (DISABLE_MDID_EVALUATION) Send a value of disabled to the PCH for the MDID field. |
28:8 | 0x0 | RW | Next Device Activity (NEXT_DEVICE_ACTIVITY) These are in 1us increments and can report a maximum value of approximately 2 seconds |
7 | 0x0 | RW | Interrupt or Memory (IM) 0: Interrupt. This is a hint for the idle duration time to the next interrupt. |
6 | 0x0 | RW | Opportunistic or Deterministic (OD) 0: Opportunistic. This is an opportunistic hint as suggested by the sub-system. |
5:2 | 0x0 | RW | RESERVED (RESERVED_BITS) Driver must write 0000b to this field. |
1 | 0x0 | RW | (VALID) 0: This Idle Duration Override CSR is not valid |
0 | 0x0 | RW | (RESERVED) Driver must write 0b to this field. |