15

0x0

RO

Detected Parity Error (DPE)

This bit is Set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. On a Function with a Type 1 Configuration
header, the bit is Set when the Poisoned TLP is received by its Primary Side.
Note: some implementations use this error type as non-fatal error indication
This bit is typically RWC. Change to RO as this bit is not in use

14

0x0

RO

Signaled System Error (SSE)

This bit is Set when a Function sends an ERR_​FATAL or ERR_​NONFATAL Message, and the SERR# Enable bit in the Command register is 1.
Note: some implementations use this error for fatal.
When received all operations are aborted.
This bit is typically RWC. Change to RO as this bit is not in use

13

0x0

RW/1C/V

Received Master Abort (RMA)

This bit is Set when a Requester receives a Completion with Unsupported Request Completion Status. On a Function with a
Type 1 Configuration header, the bit is Set when the Unsupported Request is received by its Primary Side.

12

0x0

RW/1C/V

Received Target Abort (RTA)

This bit is set when a transaction abort is received to a GMM initiated transaction

11

0x0

RW/1C/V

Signaled Target Abort (STA)

This bit is Set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function with a Type 1 Configuration header
when the Completer Abort was generated by its Primary Side.

10:8

0h

RO

Reserved

7

0x0

RO

Fast Back to Back Capable (FB2B)

Fast Back-to_​Back
(ignored by SW)

6:5

0h

RO

Reserved

4

0x1

RO

Capabilities List (CLIST)

Capability List
0: no capability list
1: the GMM contains a linked list of capabilities which is accessed via the CAPPTR register at offset 34h

3

0x0

RO/V

Interrupt Status (INTSTS)

Interrupt Status
Reflects the state of the interrupt in the device. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will this device send a virtual INTA. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit.
This bit is controlled by HW.
0: No interrupt pending
1: Interrupt pending

2:0

0h

RO

Reserved