15:8

0h

RO

Reserved

7

0x0

RW

DL_​Active ERR_​COR Enable (DLAECE)

This bit when set, enables the downstream port to signal ERR_​COR when the link transitions to the DL_​Active state.

6

0x0

RW/1S/V

DPC Software Trigger (DPCST)

If DPC Trigger is enabled and the DPC Trigger Status bit is clear, software writing a 1b to this bit will cause DPC to be triggered. If DPC Trigger is not enabled or DPC Trigger Status is set, software writing a 1b to this bit has no effect.
Note: It is permitted to write 1b to this bit while simultaneously writing updated values to other fields in this register, notably the DPC Trigger Enable field. For this case, the DPC Software Trigger semantics are based on the updated value of the DPC Trigger Enable field.
*Note: This bit always return 0b when read.

5

0x0

RW

Poisoned TLP Egress Blocking Enable (PTLPEBE)

This bit, when set, enables the associated Egress Port to block the transmission of poisoned TLP.

4

0x0

RW

DPC ERR_​COR Enable (DPCECE)

When set, this bit enables the generation of an interrupt to indicate that DPC has been triggered.

3

0x0

RW

DPC Interrupt Enable (DPCIE)

When set, this bit enables the generation of an interrupt to indicate that DPC has been triggered.

2

0x0

RW

DPC Completion Control (DPCCC)

This bit controls the Completion Status for completions formed during DPC.
0b: Completer Abort (CA) Completion Status.
1b: Unsupported Request (UR) Completion Status.

1:0

0x0

RW

DPC Trigger Enable (DPCTE)

This field enables DPC and controls the conditions that cause DPC to be triggered.
00b: DPC is disabled.
01b: DPC is enabled and is triggered when the Downstream Port detects an unmasked uncorrectable error or when the Downstream Port receives an ERR_​FATAL message.
10b: DPC is enabled and is triggered when the Downstream Port detects an unmasked uncorrectable error or when the Downstream Port receives an ERR_​NONFATAL or ERR_​FATAL message.
11b: Reserved.