12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
DPC Control Register (DPCCTLR) – Offset A06
DPC Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:8 | 0h | RO | Reserved |
7 | 0x0 | RW | DL_Active ERR_COR Enable (DLAECE) This bit when set, enables the downstream port to signal ERR_COR when the link transitions to the DL_Active state. |
6 | 0x0 | RW/1S/V | DPC Software Trigger (DPCST) If DPC Trigger is enabled and the DPC Trigger Status bit is clear, software writing a 1b to this bit will cause DPC to be triggered. If DPC Trigger is not enabled or DPC Trigger Status is set, software writing a 1b to this bit has no effect. |
5 | 0x0 | RW | Poisoned TLP Egress Blocking Enable (PTLPEBE) This bit, when set, enables the associated Egress Port to block the transmission of poisoned TLP. |
4 | 0x0 | RW | DPC ERR_COR Enable (DPCECE) When set, this bit enables the generation of an interrupt to indicate that DPC has been triggered. |
3 | 0x0 | RW | DPC Interrupt Enable (DPCIE) When set, this bit enables the generation of an interrupt to indicate that DPC has been triggered. |
2 | 0x0 | RW | DPC Completion Control (DPCCC) This bit controls the Completion Status for completions formed during DPC. |
1:0 | 0x0 | RW | DPC Trigger Enable (DPCTE) This field enables DPC and controls the conditions that cause DPC to be triggered. |