12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Egress Port Virtual Channel 1 Resource Control (EPVC1RCTL) – Offset 20
Egress Port Virtual Channel 1 Resource Control
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW | VC1 Enable (VC1E) This bit will be ignored by the hardware. The bit is R/W for specification compliance, but writing to it will result in no behavior change in the hardware (other than the bit value reflecting the written value). |
30:27 | 0h | RO | Reserved |
26:24 | 0x1 | RW | VC1 ID (VC1ID) Assigns a VC ID to the VC resource. Assigned value must be non-zero. This field can not be modified when the VC is already enabled. |
23:20 | 0h | RO | Reserved |
19:17 | 0x0 | RW | Port Arbitration Select (PAS) This field configures the VC resource to provide a particular Port Arbitration service. The default value of 0h corresponds to bit position of the only asserted bit in the Port Arbitration Capability field. |
16:8 | 0h | RO | Reserved |
7:1 | 0x0 | RW | TC/VC1 Map (TCVC1M) Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. |
0 | 0x0 | RO | TC0/VC1 Map (TC0VC1M) Traffic Class 0 is always routed to VC0. |