31:16

0h

RO

Reserved

15:8

0x0

RO/V

Fault Record Index (FRI)

This field is valid only when the PPF field is Set.

The FRI field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the PPF field was Set by hardware.

The value read from this field is undefined when the PPF field is clear.

7

0x0

RW/1C/V/P

Page Request Overflow (PRO)

Hardware detected a Page Request Overflow error. Hardware implementations not supporting the Page Request Queue implement this bit as RsvdZ.

6

0x0

RW/1C/V/P

Invalidation Time-out Error (ITE)

Hardware detected a Device-IOTLB invalidation completion time-out. At this time, a fault event may be generated based on the programming of the Fault Event Control register.

Hardware implementations not supporting device Device-IOTLBs implement this bit as RsvdZ.

5

0x0

RW/1C/V/P

Invalidation Completion Error (ICE)

Hardware received an unexpected or invalid Device-IOTLB invalidation completion. This could be due to either an invalid ITag or invalid source-id in an invalidation completion response. At this time, a fault event may be generated based on the programming of hte Fault Event Control register.

Hardware implementations not supporting Device-IOTLBs implement this bit as RsvdZ.

4

0x0

RW/1C/V/P

Invalidation Queue Error (IQE)

Hardware detected an error associated with the invalidation queue. This could be due to either a hardware error while fetching a descriptor from the invalidation queue, or hardware detecting an erroneous or invalid descriptor in the invalidation queue. At this time, a fault event may be generated based on the programming of the Fault Event Control register.
Hardware implementations not supporting queued invalidations implement this bit as RsvdZ.

3

0x0

RO/V

Advanced Pending Fault (APF)

When this field is Clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. At this time, a fault event is generated based on the programming of the Fault Event Control register.

Software writing 1 to this field clears it. Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ.

2

0x0

RO/V

Advanced Fault Overflow (AFO)

Hardware sets this field to indicate advanced fault log overflow condition. At this time, a fault event is generated based on the programming of the Fault Event Control register.

Software writing 1 to this field clears it.

Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ.

1

0x0

RO/V/P

Primary Pending Fault (PPF)

This field indicates if there are one or more pending faults logged in the fault recording registers. Hardware computes this field as the logical OR of Fault (F) fields across all the fault recording registers of this remapping hardware unit.
0: No pending faults in any of the fault recording registers.
1: One or more fault recording registers has pending faults. The FRI field is updated by hardware whenever the PPF field is set by hardware. Also, depending on the programming of Fault Event Control register, a fault event is generated when hardware sets this field.

0

0x0

RW/1C/V/P

Primary Fault Overflow (PFO)

Hardware sets this field to indicate overflow of fault recording registers. Software writing 1 clears this field. When this field is Set, hardware does not record any new faults until software clears this field.