31

0x0

RW

Translation Enable (TE)

Software writes to this field to request hardware to enable/disable DMA-remapping:
0: Disable DMA remapping.
1: Enable DMA remapping.
Hardware reports the status of the translation enable operation through the TES field in the Global Status register.
There may be active DMA requests in the platform when software updates this field. Hardware must enable or disable remapping logic only at determinstic transaction boundaries, so that any in-flight transaction is either subject to remapping or not at all.
Hardware implementations supporting DMA draining must drain any in-flight DMA read/write requests queued within the Root-Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register.
The value returned on a read of this field is undefined.

30

0x0

WO

Set Root Table Pointer (SRTP)

Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address (RTA_​REG) register.
Hardware reports the status of the Set Root Table Pointer operation through the RTPS field in the Global Status register.
The Set Root Table Pointer operation must be performed before enabling or re-enabling (after disabling) DMA remapping through the TE field.
After a Set Root Table Pointer operation, software must globally invalidate the context cache and then globally invalidate of IOTLB. This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer, and not stale cached entries.
While DMA remapping hardware is active, software may update the root table pointer through this field. However, to ensure valid in-flight DMA requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root-table pointer.
Clearing this bit has no effect. The value returned on read of this field is undefined.

29

0x0

RO

Set Fault Log (SFL)

This field is valid only for implementations supporting advanced fault logging.

Software sets this field to request hardware to set/update the fault-log pointer used by hardware. The fault-log pointer is specified through Advanced Fault Log register.
Hardware reports the status of the Set Fault Log operation through the FLS field in the Global Status register.

The fault log pointer must be set before enabling advanced fault logging (through EAFL field). Once advanced fault logging is enabled, the fault log pointer may be updated through this field while DMA remapping is active.
Clearing this bit has no effect. The value returned on read of this field is undefined.

28

0x0

RO

Enable Advanced Fault Logging (EAFL)

This field is valid only for implementations supporting advanced fault logging.
Software writes to this field to request hardware to enable or disable advanced fault logging:
0: Disable advanced fault logging. In this case, translation faults are reported through the Fault Recording registers.
1: Enable use of memory-resident fault log. When enabled, translation faults are recorded in the memory-resident log. The fault log pointer must be set in hardware (through the SFL field) before enabling advaned fault logging. Hardware reports the status of the advaned fault logging enable operation through the AFLS field in the Global Status register.
The value returned on read of this field is undefined.

27

0x0

RO

Write Buffer Flush (WBF)

This bit is valid only for implementations requiring write buffer flushing.
Software sets this field to request that hardware flush the Root-Complex internal write buffers. This is done to ensure any updates to the memory-resident remapping structures are not held in any internal write posting buffers.
Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register.
Clearing this bit has no effect. The value returned on a read of this field is undefined.

26

0x0

RW

Queued Invalidation Enable (QIE)

This field is valid only for implementations supporting queued invalidations.
Software writes to this field to enable or disable queued invalidations.
0: Disable queued invalidations.
1: Enable use of queued invalidations.

Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register.
The value returned on a read of this field is undefined.

25

0x0

RW

Interrupt Remapping Enable (IRE)

This field is valid only for implementations supporting interrupt remapping.
0: Disable interrupt-remapping hardware.
1: Enable interrupt-remapping hardware.
Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register.
There may be active interrupt requests in the platform when software updates this field. Hardware must enable or disable interrupt-remapping logic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to remapping or not at all.
Hardware implementations must drain any in-flight interrupts requests queued in the Root-Complex before completing the interrupt-remapping enable command and reflecting the status of the command through the IRES field in the Global Status register.
The value returned on a read of this field is undefined.

24

0x0

WO

Set Interrupt Remap Table Pointer (SIRTP)

This field is valid only for implementations supporting interrupt-remapping.
Software sets this field to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address (IRTA_​REG) register.
Hardware reports the status of the Set Interrupt Remap Table Pointer operation through the IRTPS field in the Global Status register.
The Set Interrupt Remap Table Pointer operation must be performed before enabling or re-enabling (after disabling) interrupt-remapping hardware through the IRE field.
After a Set Interrupt Remap Table Pointer operation, software must globally invalidate the interrupt entry cache. This is required to ensure hardware uses only the interrupt-remapping entries referenced by the new interrupt remap table pointer, and not any stale cached entries.
While interrupt remapping is active, software may update the interrupt remapping table pointer through this field. However, to ensure valid in-flight interrupt requests are deterministically remapped, software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read of this field is undefined.

23

0x0

RW

Compatibility Format Interrupt (CFI)

This field is valid only for Intel64 implementations supporting interrupt-remapping.
Software writes to this field to enable or disable Compatibility Format interrupts on Intel64 platforms. The value in this field is effective only when interrupt-remapping is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
0: Block Compatibility format interrupts.
1: Process Compatibility format interrupts as pass-through (bypass interrupt remapping).

Hardware reports the status of updating this field through the CFIS field in the Global Status register.
The value returned on a read of this field is undefined.

22:0

0h

RO

Reserved