15:8

0x5

RW/L

(GMS)

This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
This register is also Intel TXT lockable.
Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled.
BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) is 0.

7:6

0x0

RW/L

(GGMS)

This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS needs to allocate a contiguous memory chunk. Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register.
Hardware functionality in case of programming this value to Reserved is not guaranteed.

5:3

0h

RO

Reserved

2

0x0

RW/L

(VAMEN)

Enables the use of the iGFX engines for Versatile Acceleration.
1 - iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 038000h.
0 - iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h.

1

0x0

RW/L

(IVD)

0: Enable. Device 2 (IGD) claims VGA memory and IO cycles
1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO)
BIOS Requirement : If a value of 1 is written, GGC[VAMEN] (ie. bit 2 in this register) should be also written to '1 so the sub-class field changes to 80.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 7:3 of this register) pre-allocates no memory.

0

0x0

RW/L

(GGCLCK)

When set to 1b, this bit will lock all bits in this register.