Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) – Offset 10 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) – Offset 10

This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 16 MB combined for MMIO and Global GTT aperture, with 2MB of that used by MMIO, 6MB reserved, and 8MB used by GTT. GTTADR will begin at (GTTMMADR + 8 MB) while the MMIO base address will be the same as GTTMMADR. The region between (GTTMMADR + 2MB) - (GTTMMADR + 8MB) is reserved. For the Global GTT, this range is defined as a memory BAR in graphics device configuration space. It is an alias into which software is required to write Page Table Entry values (PTEs). Software may read PTE values from the global Graphics Translation Table (GTT). PTEs cannot be written directly into the global GTT memory area. The device snoops writes to this region in order to invalidate any cached translations within the various TLBs implemented on-chip. The allocation is for 16MB and the base address is defined by bits [38:24].

Bit Range	Default	Access	Field Name and Description
31:24	0x0	RW/V	Memory Base Address (MBA_0) Set by the OS, these bits correspond to address signals [63:24].
23:4	0x0	RO	Address Mask (ADM) Hardwired to 0s to indicate at least 16MB address range.
3	0x0	RO	Prefetchable Memory (PREFMEM) Hardwired to 0 to prevent prefetching.
2:1	0x2	RO	Memory Type (MEMTYP) Hardwired to 2h to indicate 64 bit base address.
0	0x0	RO	Memory I/O Space (MIOS) Hardwired to 0 to indicate memory space.

Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI)

Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI)