I/O Base Address (IOBAR_0_2_0_PCI) – Offset 20 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

I/O Base Address (IOBAR_0_2_0_PCI) – Offset 20

This register provides the Base offset of the I/O registers within Device #2.
Bits 15:6 are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address Space.
Bits 2:1 are fixed and return zero
Bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded.
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.
Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if Internal graphics is disabled.
Note that access to this IO BAR is independent of VGA functionality within Device #2.
If accesses to this IO bar is allowed then all 8, 16 or 32 bit IO cycles from IA cores that falls within the 8B are claimed.
This IO BAR can be disabled and hidden from system software via DEV2CTL[0] IOBARDIS at offset 0x58.

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved
15:6	0x0	RW/V/L	IO Base Address (IOBASE) Set by the OS, these bits correspond to address signals [15:6]. Note: This field is RO 0's if DEV2CTL[0] IOBARDIS is 1b.
5:3	0h	RO	Reserved
2:1	0x0	RO	Memory Type (MEMTYPE) Hardwired to 0s to indicate 32-bit address.
0	0x1	RO	Memory I/O Space (MIOS) Hardwired to '1' to indicate IO space. Note: This field is RO 0's if DEV2CTL[0] IOBARDIS is 1b.

Subsystem Vendor ID (SVID2_0_2_0_PCI)

Graphics Memory Range Address (GMADR1_0_2_0_PCI) Subsystem Vendor ID (SVID2_0_2_0_PCI)