63

0x0

RW/V

Invalidate IOTLB (IVT)

Software requests IOTLB invalidation by setting this field. Software must also set therequested invalidation granularity by programming the IIRG field
Hardware clears the IVT field to indicate the invalidation request is complete. Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field. Software must not submit another invalidation request through this register while the IVT field is Set, nor update the associated Invalidate Address register
Software must not submit IOTLB invalidation requests when there is a context-cache invalidation request pending at this remapping hardware unit.

Hardware implementations reporting write-buffer flushing requirement (RWBF=1 in Capability register) must implicitly perform a write buffer flushing before invalidating the IOTLB.

62

0h

RO

Reserved

61:60

0x0

RW

IOTLB Invalidation Request Granularity (IIRG)

When requesting hardware to invalidate the IOTLB (by setting the IVT field), software writes the requested invalidation granularity through this field. The following are the encodings for the field
0: Reserved
1: Global invalidation request
2: Domain-selective invalidation request. The target domain-id must be specified in the DID field
3: Page-selective invalidation request. The target address, mask and invalidation hint must be specified in the Invalidate Address register, and the domain-id must be provided in the DID field
Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested. Hardware indicates completion of the invalidation request by clearing the IVT field. At this time, the granularity at which actual invalidation was performed is reported through the IAIG field.

59

0h

RO

Reserved

58:57

0x1

RO/V

IOTLB Actual Invalidation Granularity (IAIG)

Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field). The following are the encodings for this field
0: Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request. Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page-selective invalidation requests
1: Global Invalidation performed. This could be in response to a global, domain-selective, or page-selective invalidation request
2: Domain-selective invalidation performed using the domain-id specified by software in the DID field. This could be in response to a domain-selective or a page-selective invalidation request
3: Domain-page-selective invalidation performed using the address, mask and hint specified by software in the Invalidate Address register and domain-id specified in DID field. This can be in response to a page-selective invalidation request.

56:50

0h

RO

Reserved

49

0x0

RW

Drain Reads (DR)

This field is ignored by hardware if the DRD field is reported as clear in the Capability register. When the DRD field is reported as Set in the Capability register, the following encodings are supported for this field:
0: Hardware may complete the IOTLB invalidation without draining any translated DMA read requests.
1: Hardware must drain DMA read requests.

48

0x0

RW

Drain Writes (DW)

This field is ignored by hardware if the DWD field is reported as Clear in the Capability register. When the DWD field is reported as Set in the Capability register, the following encodings are supported for this field:
0: Hardware may complete the IOTLB invalidation without draining DMA write requests.
1: Hardware must drain relevant translated DMA write requests.

47:32

0x0

RW

Domain ID (DID)

Indicates the ID of the domain whose IOTLB entries need to be selectively invalidated. This field must be programmed by software for domain-selective and page-selective invalidation requests.

The Capability register reports the domain-id width supported by hardware. Software must ensure that the value written to this field is within this limit. Hardware ignores and not implements bits 47:(32+N), where N is the supported domain-id width reported in the Capability register.

31:0

0h

RO

Reserved