31:24

0h

RO

Reserved

23:19

0x5

RW/O

Port Tpower_​on Value (PTV)

Along with the Port Tpower_​on Scale field in the L1 Sub-states Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.OFF_​EXIT after sampling CLKREQ# asserted before actively driving the interface.
Port Tpower_​on is calculated by multiplying the value in this field by the value in the Port Tpower_​on scale field in the L1 Sub-States Capabilities register.
Required for all Ports that support L1.OFF

18

0h

RO

Reserved

17:16

0x0

RW/O

Port Tpower_​on Scale (PTPOS)

Specifies the scale used for Tpower_​on value field in the L1 Sub-states Capabilities register.
00b: 2 us
01b: 10 us
10b: 100 us
11b: Reserved
Required for all Ports that support L1.OFF

15:8

0x28

RW/O

Port Common Mode Restore Time (PCMRT)

This is the time (in us) required for this Port to re-establish common mode.
Required for all ports that support L1.OFF.

7

0h

RO

Reserved

6

0x0

RW/1C/V

CLKREQ# Acceleration Interrupt Status (L1SSEIS)

For a Downstream Port that has both the CLKREQ# Acceleration Supported and CLKREQ# Acceleration Interrupt Enable bits Set, when set this bit indicates that the Port has completed the CLKREQ# Acceleration Link Activation process, and that the Link has reached L0. Software must then clear this bit by writing a 1b to this bit.
Must be hardwired to 0b for Upstream Ports.
Default value is 0b.

5

0x0

RW/O

CLKREQ# Acceleration Supported (L1SSES)

When set this bit indicates that this Port supports CLKREQ# acceleration.

4

0x1

RW/O

L1 PM Sub-states Supported (L1PSS)

When Set this bit indicates that this Port supports L1 PM Sub-states.
For compatibility with possible future extensions, software must not enable L1 PM Sub-states unless this bit is set.
This RWO field must be programmed prior to enabling ASPM.
Required for both Upstream and Downstream Ports.

3

0x1

RW/O

ASPM L1.1 Supported (AL11S)

When set, this bit indicates ASPM L1.SNOOZ is supported.
Required for both Upstream and Downstream ports.
This RWO field must be programmed prior to enabling ASPM.

2

0x1

RW/O

ASPM L1.2 Supported (AL12S)

When set, this bit indicates that ASPM L1.OFF is supported.
Required for both Upstream and Downstream ports.
This RWO field must be programmed prior to enabling ASPM.

1

0x1

RW/O

PCI-PM L1.1 Supported (PPL11S)

When set, this bit indicates that PCI-PM L1.SNOOZ is supported and this bit must be set by all ports implementing L1 Sub-States. A port that supports L1.OFF must support L1.SNOOZ.
Required for both upstream and downstream ports.
This RWO field must be programmed prior to enabling ASPM.

0

0x1

RW/O

PCI-PM L1.2 Supported (PPL12S)

When set, this bit indicates that PCI-PM L1.OFF is supported.
Required for both upstream and downstream ports.
This RWO field must be programmed prior to enabling ASPM.