31:25

0h

RO

Reserved

24

0x1

RW/O

Two Retimers Presence Detect Supported (TRPDS)

When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.
This bit must be set to 1b in a Downstream Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher. It is permitted to be set to 1b regardless of the supported Link speeds, and in Upstream Ports, if the Retimer Presence Detect Supported bit is also set to 1b.

23

0x1

RW/O

Retimer Presence Detect Supported (RPDS)

When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.
This bit must be set to 1b in a Downstream Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher. It is permitted to be set to 1b regardless of the supported Link speeds and in Upstream Ports.

22:16

0x0

RW/O

Lower SKP OS Reception Supported Speeds Vector (LSOSRSS)

If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS.
Bit definitions within this field are:
Bit 0 2.5 GT/s
Bit 1 5.0 GT/s
Bit 2 8.0 GT/s
Bit 3 16.0 GT/s
Bits 6:4 RsvdP
Behavior is undefined if a bit is set in this field and the corresponding bit is not set in the Supported Link Speeds Vector.
This register is Read-Only if LPCR.SRL field is set.

15:9

0x0

RW/O

Lower SKP OS Generation Supported Speeds Vector (LSOSGSSV)

If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate.
Bit definitions within this field are:
Bit 0 2.5 GT/s
Bit 1 5.0 GT/s
Bit 2 8.0 GT/s
Bit 3 16.0 GT/s
Bits 6:4 RsvdP
Behavior is undefined if a bit is set in this field and the corresponding bit is not set in the Supported Link Speeds Vector.
This register is Read-Only if LPCR.SRL field is set.

8

0x0

RO

Crosslink Supported (CS)

No support for Crosslink.

7:1

0x7

RO/V

Supported Link Speeds Vector (SLSV)

This field indicates the supported Link speed of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported - otherwise, the Link speed is not supported.
Bit definitions within this field for PCI Express are:
Bit 0: 2.5 GT/s.
Bit 1: 5.0 GT/s.
Bit 2: 8.0 GT/s.
Bit 3: 16.0 GT/s.
Bit 4: 32.0 GT/s.
Bits 5-6: Reserved.

0

0h

RO

Reserved