31:16

0h

RO

Reserved

15:9

0x0

RW

Enable Lower SKP OS Generation Vector (ELSOSGV)

When the Link is in L0 and the bit in this field corresponding to the current Link speed is Set, SKP Ordered Sets are scheduled at the rate defined for SRNS, overriding the rate required based on the clock tolerance architecture.
Bit definitions within this field are:
Bit 0 2.5 GT/s
Bit 1 5.0 GT/s
Bit 2 8.0 GT/s
Bit 3 16.0 GT/s
Bits 6:4 Rsvd
Behavior is undefined if a bit is Set in this field and the corresponding bit in the Lower SKP OS Generation Supported Speeds Vector is not set.

8:2

0h

RO

Reserved

1

0x0

RW/P

Link Equalization Request Interrupt Enable (LERIE)

When set, this bit enables the generation of an interrupt to indicate that the Link Equalization Request bit has been set.
Register Attribute: Dynamic.

0

0x0

RW/1S/V

Perform Equalization (PE)

When this bit is 1b and Link Retrain bit is set with the Target Link Speed field set to 8 GT/s, the Downstream Port must perform Link Equalization.
This bit is cleared by Root Port upon entry to Link Equalization Phase 1.
Register Attribute: Dynamic.