15:8

0h

RO

Reserved

7

0x0

RO/V/P

Two Retimers Presence Detected (PX2RPD)

When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation.
The default value of this bit is 0b.
This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.
Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.

6

0x0

RO/V/P

Retimer Presence Detected (RPD)

When set to 1b, the LTSSM is required to send SKP Ordered Sets periodically in between the (modified) compliance patterns.
The default value of this bit is 0b.
This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.

5

0x0

RW/1C/V/P

Link Equalization Request (LER)

This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link.

4

0x0

RO/V/P

Equalization Phase 3 Successful (EQP3S)

When set to 1, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed.

3

0x0

RO/V/P

Equalization Phase 2 Successful (EQP2S)

When set to 1, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed.

2

0x0

RO/V/P

Equalization Phase 1 Successful (EQP1S)

When set to 1, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed.

1

0x0

RO/V/P

Equalization Complete (EQC)

When set to 1, this bit indicates that the Transmitter Equalization procedure at the 8.0GT/s data rate has completed.

0

0x0

RO/V

Current De-emphasis Level (CDL)

When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.
Encodings:
1b -3.5 dB
0b -6 dB
The value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.