31

0x0

RW

RUN/BUSY Bit (RUN_​BUSY)

This bit indicates that the BIOS request is pending.
BIOS sets this bit together with a command in the lower bits of this register.
The PCU may only clear this bit after the BIOS request has completed.

30:27

0x0

RW

Request VDDQ TX IccMax (REQ_​VDDQ_​TX_​ICCMAX)

Peak current on VDDQTX rail at this clock frequency and gear configuration. Described in 0.25A resolution. Max: 32 * 0.25 = 8A;

26:17

0x0

RW

Request VDDQ TX Voltage (REQ_​VDDQ_​TX_​VOLTAGE)

Voltage of the VDDQTX rail at this clock frequency and gear configuration. Described in 5mV resolution.

16:14

0h

RO

Reserved

13:12

0x0

RW

Gear Type (GEAR)

0: Gear1 (Default) - DDR bus clock is the same as QCLK
1: Gear2 - DDR PHY bus clock is double of QCLK
2: Gear4 - DDR PHY bus clock is quad of QCLK

11:8

0x0

RW

Reference Clock Type (MC_​PLL_​REF)

Request Type:
0: MC frequency request for 133MHz Qclk granularity.
1: MC frequency request for 100MHz Qclk granularity.
All other values are reserved.

7:0

0x0

RW

MC PLL Ratio (MC_​PLL_​RATIO)

This field holds the memory controller frequency request (QCLK). Each bin is 133/100MHz and not 266/200MHz.
This interface replaces the usage of DCLK ratios and Odd Ratio.
QCLK frequency is determined by the MC reference clock (MC_​FREQ_​TYPE) as well as BCLK.
Binary Dec DCLK Equation DCLK Freq QCLK Equation QCLK Freq
0000b 0d ------------------------------------ MC PLL - shutdown --------------------------------------------
...
0011b 3d 3 * 66.66 200.00 MHz 3 * 133.33 400.00 MHz
0100b 4d 4 * 66.66 266.66 MHz 4 * 133.33 533.33 MHz
0101b 5d 5 * 66.66 333.33 MHz 5 * 133.33 666.67 MHz
0110b 6d 6 * 66.66 400.00 MHz 6 * 133.33 800.00 MHz
0111b 7d 7 * 66.66 466.66 MHz 7 * 133.33 933.33 MHz
1000b 8d 8 * 66.66 533.33 MHz 8 * 133.33 1066.67 MHz
...