Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) – Offset D840 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) – Offset D840

Counts every 64B memory read and write request entering the Memory Controller to DRAM (sum of all channels).
Each write request counts as a new request incrementing this counter.
However, same-cache-line write requests (both full and partial) are combined to a single 64-byte data transfer to DRAM.
Therefore multiplying the number of requests by 64-bytes will lead to inaccurate memory bandwidth.
The inaccuracy is proportional to the number of same-cache-line writes.
If a SOC has multiple MCs instantiated, all instances of this counter will need to be added together to get total memory request bandwidth.

Bit Range	Default	Access	Field Name and Description
63:0	0x0	RW/V	Request Count (count) Count of the total number of 64B CMI read and write requests entering this MC.

Bit Range

Default

Access

Field Name and Description

63:0

0x0

RW/V

Request Count (count)

Count of the total number of 64B CMI read and write requests entering this MC.

RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)

Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR) RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)