63:27

0h

RO

Reserved

26:24

0x0

RW

(HASH_​LSB_​MASK_​BIT)

HASH_​LSB_​MASK_​BIT
This specifies the memory slice interleave bit. The following encoding is used:
000 - Addr[6]
001 - Addr[7]
010 - Addr[8]
011 - Addr[9]
100 - Addr[10]
101 - Addr[11]
110 - Addr[12]
111 - Addr[13]
For example, setting this field to 10b will interleave the slices at a 4 cacheline granularity. BIOS should set this field same as the lowest selected bit in the HASH_​MASK field of this CR. Note that if the HASH_​MASK field does not include the corresponding interleave bit, it will still be included in teh XOR function by the memory slice decoding logic.

23:20

0h

RO

Reserved

19:6

0x1

RW

(HASH_​MASK)

HASH_​MASK
The 14-bit mask corresponds to memory request Addr[19:6]. Setting a mask bit to 1 will include that particular address bit in the slice XOR function. For example, if the mask is set to 14'h0C04, then Slice = Addr[17] ^ Addr[16] ^ Addr[8].
Channel selection in the dual-channel range:
Channel = Bitwise-xor(addr{19:6} & mask{19:6})
Bitwise AND mask with Address bits to be XORED.
Conditions apply:
HASH_​MASK configuration must clear all bits below the MASK_​LSB value
HASH_​MASK configuration must set 1 on MASK_​LSB location

5:4

0h

RO

Reserved

3:0

0x4

RW

(MC_​org)

0: Single MC - MC0
1: Single MC - MC1
2: Dual MC L-shape - MC0 > MC1
3: Dual MC L-shape - MC1 > MC0
4: Dual MC, no L-shape