31

0x1

RW

Interrupt Mask (IM)

Interrupt Mask
0: No masking of interrupt. When a page request event condition is detected, hardware issues an interrupt message (using the Page Request Event Data and Page Request Event Address register values).
1: This is the value on reset. Software may mask interrupt message generation by setting this field. Hardware is prohibited from sending the interrupt message when this field is Set.

30

0x0

RO/V

Interrupt Pending (IP)

Interrupt Pending: Hardware sets the IP field whenever it detects an interrupt condition. Interrupt condition is defined as:
A streaming page request entry (page_​stream_​req_​dsc) or a page group request (page_​grp_​req_​dsc) with Last Page in Group (LPG) field Set, was added to page request queue, resulting in hardware setting the Pending Page Request (PPR) field in Page Request Status register
If the PPR field in the Page Request Event Status register was already Set at the time of setting this field, it is not treated as a new interrupt condition
The IP field is kept Set by hardware while the interrupt message is held pending. The interrupt message could be held pending due to interrupt mask (IM field) being Set, or due to other transient hardware conditions. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced. This could be due to either:

• Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field
  
• Software servicing the PPR field in the Page Request Event Status register.

29:0

0h

RO

Reserved