12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
PASID Control (PASID_CTRL_0_2_0_PCI) – Offset 106
Process Address Space ID (PASID) control for Device-2.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:3 | 0h | RO | Reserved |
2 | 0x0 | RO | Privileged Mode Enable (PME) Hardwired to 0, the Endpoint is not permitted to request privileged mode in requests-with-PASID. |
1 | 0x0 | RW | Execute Permission Enable (EPE) If Set, the Endpoint is permitted to request execute permission in requests-with-PASID. If Clear, the Endpoint is not permitted to do so. Behavior is undefined if this bit changes value when ATS Enable field in ATS Capability is Set.Processor graphics does not use this field. Software is expected to Set this field before configuring extended-context-entry for Device-2 with the Execute Request Enable field Set. |
0 | 0x0 | RW | PASID Enable (PE) If Set, the Endpoint is permitted to generate requests-with-PASID. If Clear, the Endpoint is not permitted to do so. Behavior is undefined if this bit changes value when ATS Enable field in ATS Capability is Set. If privileged Mode Supported field in PASID Capability register is Clear, then this field is treated as Reserved(0).Processor graphics does not use this field. Software is expected to Set this field before configuring extended-context-entry for Device-2 with Supervisor Request Enable field Set. For compatibility reasons, this field is implemented as RW. |