15:6

0h

RO

Reserved

5

0x0

RO

Transactions Pending (TP)

When Set, this bit indicates that the Function has issued Non-Posted Requests that have not been completed.A Function reports this bit is cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.

4

0x0

RO

Aux Power Detected (APD)

Functions that require Aux power report this bit as Set if Aux power is detected by the Function. Hardwired to 0b, the integrated graphics device does not require Aux power.

3

0x0

RO

Unsupported Request Detected (URD)

This bit indicates the Function received an Unsupported Request.Hardwired to 0b, the Root Complex Integrated Endpoint graphics device does not use the PCI Express error reporting mechanism.

2

0x0

RW/V

Fatal Error Detected (FED)

This bit indicates status of fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.

1

0x0

RW/V

Non-Fatal Error Detected (NFED)

This bit indicates status of non fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.

0

0x0

RW/V

Correctable Error Detected (CED)

This bit indicates status of correctable errors detected.
Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.