15

0x0

RW/V

Initiate Function Level Reset (INIT_​FLR)

A write of 1b initiates Function Level Reset to the Function.During FLR, a read will return 1b since device 2 reads abort. If a local panel is powered on and configured to power down on reset, the FLR will typically take several hundred milliseconds to complete. The worst possible, although unrealistic, delay is 5 seconds.

14:12

0x0

RO

Max Read Request Size (MRRS)

Functions that do not generate Read Requests larger than 128 bytes and Functions that do not generate Read Requests on their own behalf are permitted to implement this field as Read Only (RO) with a value of 000b.

11

0x0

RO

Enable No Snoop (ENS)

This bit is permitted to be hardwired to 0b if a Function would never Set the No Snoop attribute in transactions it initiates.The graphics device never generates a PCI Express TLP.

10

0x0

RO

Aux Power PM Enable (APPME)

Functions that do not implement this capability hardwire this bit to 0b.

9

0x0

RO

Phantom Functions Enable (PFE)

Functions that do not implement this capability hardwire this bit to 0b.

8

0x0

RO

Extended Tag Field Enable (ETFE)

Functions that do not implement this capability hardwire this bit to 0b.

7:5

0x0

RO

Max Payload Size (MPS)

Functions that support only the 128-byte max payload size are permitted to hardwire this field to 000b.

4

0x0

RO

Enable Relaxed Ordering (ERO)

A Function is permitted to hardwire this bit to 0b if it never sets the Relaxed Ordering attribute in transactions it initiates as a Requester.The graphics device never generates a PCI Express TLP.

3

0x0

RO

Unsupported Request Response Enable (URRE)

A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b.

2

0x0

RW/V

Fatal Error Enable (FEE)

This bit, in conjunction with other bits, controls sending ERR_​FATAL Messages.

1

0x0

RW/V

Non-Fatal Error Enable (NFEE)

This bit, in conjunction with other bits, controls sending ERR_​NONFATAL Messages.

0

0x0

RW/V

Correctable Error Enable (CEE)

This bit, in conjunction with other bits, controls sending ERR_​COR Messages.