Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) – Offset AC4 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) – Offset AC4

Physical Layer 16.0 GT/s Lane 89 Equalization Control Register

Bit Range	Default	Access	Field Name and Description
15:12	0xF	RW	Upstream Port 16 GT/s Port Lane 9 Transmitter Preset (UP16L9TP) Field contains the Transmit Preset value sent or received during Port 16 GT/s Link Equalization. Port Direction: Downstream Port Crosslink Supported: Any Usage: Contains value sent on the associated Lane during Link EQ
11:8	0xF	RW	Downstream Port 16 GT/s Lane 9 Transmitter Preset (DP16L9TP) Transmitter Preset used for 16 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port.
7:4	0xF	RW	Upstream Port 16 GT/s Port Lane 8 Transmitter Preset (UP16L8TP) Field contains the Transmit Preset value sent or received during Port 16 GT/s Link Equalization. Port Direction: Downstream Port Crosslink Supported: Any Usage: Contains value sent on the associated Lane during Link EQ.
3:0	0xF	RW	Downstream Port 16 GT/s Lane 8 Transmitter Preset (DP16L8TP) Transmitter Preset used for 16 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port.

Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)

Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)