12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Physical Layer 16.0 GT/s Lane9 Margin Control and Status (PL16L9MCS) – Offset F08
Physical Layer 16.0 GT/s Lane9 Margin Control and Status
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0x0 | RO/V | Margin Payload Status (MPSTS) This field is only meaningful, when the Margin Type |
23 | 0h | RO | Reserved |
22 | 0x0 | RO/V | Usage Model Status (UMS) This field must be reset to the default value if the Port goes to DL_Down status. |
21:19 | 0x0 | RO/V | Margin Type Status (MTS) This field must be reset to the default value if the Port goes to DL_Down status. |
18:16 | 0x0 | RO/V | Receiver Number Status (RNS) This field must be reset to the default value if the Port goes to DL_Down status. |
15:8 | 0x9C | RW | Margin Payload (MP) This fields value is used in conjunction with the Margin Type field. |
7 | 0h | RO | Reserved |
6 | 0x0 | RW | Usage Model (UM) The default value is 0b. |
5:3 | 0x7 | RW | Margin Type (MT) The default value is 111b. |
2:0 | 0x0 | RW | Receiver Number (RN) The default value is 000b. |