12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23) – Offset EE2
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:2 | 0h | RO | Reserved |
1 | 0x0 | RO/V | Margining Software Ready (MARGINSWRDY) When Margining uses Driver Software is Set, then this bit, when Set, indicates that the required software has performed the required initialization. The value of this bit is Undefined if Margining users Driver Software is Clear. |
0 | 0x0 | RO/V | Margining Ready (MARGINRDY) Indicates when the Margining feature is ready to accept margining commands. Behavior is undefined if this bit is Clear and, for any Lane, any of the Receiver Number, Margin Type, Usage Model, or Margin Payload fields are written. |