Physical Layer 32.0 GT/s Control (G5CTL) – Offset AE4 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Physical Layer 32.0 GT/s Control (G5CTL) – Offset AE4

Physical Layer 32.0 GT/s Control

Bit Range	Default	Access	Field Name and Description
31:11	0h	RO	Reserved
10:8	0x0	RW/P	Modified TS Usage Mode Selected (MODTSUSGSEL) When Clear, this Port indicates during Link Training that is wishes to train to the highest common link data rate and skip equalization of intermediate data rates. Equalization bypass to highest rate Supported is Set, this bit is RWS with a default value of 0b. Equalization bypass to highest rate Supported is Clear, this bit is permitted to be hardwired to 0b.
7:2	0h	RO	Reserved
1	0x1	RW/P	No Equalization Needed Disable (NOEQDIS) When Clear, this Port is permitted to indicate that it does not require equalization. When Set, this Port must always indicate that it requires equalization. No Equalization Needed Supported is Set, this bit is RWS with a default value of 0b. No Equalization Needed Supported is Clear, this bit is permitted to be hardwired to 0b. If this bit is Set, Equalization bypass to highest rate Disable must also be Set.
0	0x0	RW/P	Equalization bypass to highest rate Disable (EQBYPDIS) When Clear, this Port indicates during Link Training that is wishes to train to the highest common link data rate and skip equalization of intermediate data rates. Equalization bypass to highest rate Supported is Set, this bit is RWS with a default value of 0b. Equalization bypass to highest rate Supported is Clear, this bit is permitted to be hardwired to 0b.

Physical Layer 32.0 GT/s Status (G5STS)

Physical Layer 32.0 GT/s Capability (G5CAP) Physical Layer 32.0 GT/s Status (G5STS)