Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) – Offset ADC - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) – Offset ADC

Physical Layer 32.0 GT/s Extended Capability Header

Bit Range	Default	Access	Field Name and Description
31:20	0x0	RW/O	Next Capability Offset (NCO) This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh. Note: Lock Key bit is located in the Personality Lock Key Control Register. Software will need to program this field appropriately for linked capabilities list if default is not supported.
19:16	0x0	RW/O	Capability Version (CV) This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. Must be 1h for this version of the specification.
15:0	0x2A	RW/O	PCI Express Extended Capability ID (ECID) This field is a PCISIG defined ID number that indicates the nature and format of the Extended Capability. The Extended Capability ID for the Physical Layer 32.0 GT/s Capability is 002Ah.

Bit Range

Default

Access

Field Name and Description

31:20

0x0

RW/O

Next Capability Offset (NCO)

This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.
For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.
Note: Lock Key bit is located in the Personality Lock Key Control Register.
Software will need to program this field appropriately for linked capabilities list if default is not supported.

19:16

0x0

RW/O

Capability Version (CV)

This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
Must be 1h for this version of the specification.

15:0

0x2A

RW/O

PCI Express Extended Capability ID (ECID)

This field is a PCISIG defined ID number that indicates the nature and format of the Extended Capability.
The Extended Capability ID for the Physical Layer 32.0 GT/s Capability is 002Ah.

Physical Layer 32.0 GT/s Capability (G5CAP)

Physical Layer 16.0 GT/s Lane 1415 Equalization Control (PL16L1415EC) Physical Layer 32.0 GT/s Capability (G5CAP)