PM Base Address (PM_BAR) – Offset 10 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

PM Base Address (PM_BAR) – Offset 10

Base address register.

Bit Range	Default	Access	Field Name and Description
63:39	0h	RO	Reserved
38:15	0x0	RW	PMBAR Address (PMBAR) This field corresponds to bits 38 to 15 of the base address PMBAR address space. BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space. This register ensures that a naturally aligned 32KB space is allocated within total addressable memory space.
14:4	0x0	RO	Address Mask (ADDRESS_MASK) Hardwired to 0s to indicate at least 32KB address range. Software typically writes all 1's to the BAR and then reads back the resulting value to assess the size of the BAR. Since bits 14:4 are read-only and zero, that indicates that the device is 32KB.
3	0x0	RO	BAR is Prefetchable (PREFETCHABLE) Value of 0 indicates the BAR cannot be prefetched.
2:1	0x2	RO	Address Range (ADDRESS_RANGE) Address Range: Value of 0x2 indicates that the BAR is located anywhere system memory space (i.e. 64-bit addressing). This also indicates that the size of the BAR register is 64b.
0	0x0	RO	Memory Space Indicator (SPACE_TYPE) Value of 0 indicates the BAR is located in memory space.

Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID)

Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE) Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID)