63:59

0x1

RW

tPRPDEN Timing Parameter (tPRPDEN)

This this register covers Any CMD --> PDE timing in tCK (WCK for LPDDR5)
Note this register must be programmed to a minimum of 4 in Gear2 and a minimum of 2 in Gear1
Note for LP4 and LP5, program as follows.
LPDDR4: tCMDPDE + 2
LPDDR5: tCMDPDE + 4

58:54

0h

RO

Reserved

53:48

0x4

RW

tCSL Timing Parameter (tCSL)

Chip Select low pulse width on power down exit (specified in DCLKs) :this is a fixed spec value (and in LPDDR5 this value is in resolution of tCK or multiples of 4WCK) and the value programmed in the register is in MC DCLKs / WCK
Note: it should also be noted that tCSL covers for both tCSL and tCSCAL in LPDDR5.

47:42

0x4

RW

tCSH Timing Parameter (tCSH)

Chip Select high pulse width on power down exit (specified in DCLKs): this is a fixed spec value (and LPDDR5 this value is in resolution of tCK or multiples of 4WCK) .The Final value programmed in the register is in MC DCLKs/WCK

41:32

0x4

RW

tWRPDEN Timing Parameter (tWRPDEN)

Holds DDR timing parameter tWRPDEN.
WR to power down minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-204.

31:29

0h

RO

Reserved

28:21

0x4

RW

tRDPDEN Timing Parameter (tRDPDEN)

Holds DDR timing parameter for tRDPDEN.
RD to power down minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-100.
Notes:
Because CKE power down is asynchrnous CKE may drop on the negative edge of the clock, an increase of +1 is needed for LPDDR4.
An additional increase of +1 is needed in the formula for LPDDR4

20:14

0x4

RW

tXP Timing Parameter (tXPDLL)

Holds DDR timing parameter tXP.
Power up to RD/WR minimum delay in tCK (WCK for LPDDR5) cycles.
Applicable for DDR4 in case of exit from PPD when DRAM is configured to slow-exit mode.
Supported range is 4-63.

13:7

0x4

RW

tXP Timing Parameter (tXP)

Holds DDR timing parameter tXP.
Power up to any command minimum delay in tCK /WCK cycles.
Supported range is 4-24.

6:0

0x4

RW

tCKE Timing Parameter (tCKE)

Holds DDR timing parameter tCKE.
Power down to power up (and vice versa) minimum delay in tCK (WCK for LPDDR5) cycles.
Note that for LPDDR4 this value is also used for tCKCKEL and tCKELCMD.
Supported range is 4-24.