31:27

0x0

RO

PME Support (PME_​SUPPORT)

This field indicates the power states in which the device may assert PME#. It is hardwired to 0 to indicate that the device does not support nor assert the PME# signal.

26

0x0

RO

(D2)

Hardwired to 0 to indicate that the D2 power management state is not supported.

25

0x0

RO

(D1)

Hardwired to 0 to indicate that the D1 power management state is not supported.

24:22

0h

RO

Reserved

21

0x0

RO

Device Specific Initialization (DEVICE_​SPECIFIC_​INITIALIZATION)

Indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it.
This bit is not used by some operating systems.
Windows OS, for instance, does not use this bit to determine whether to use D3. Instead, they use the driver's capabilities to determine this.
1b indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialized state.

20

0h

RO

Reserved

19

0x0

RO

PME Capability (PME_​CAPABILITY)

When this bit is set, it indicates that the function relies on the presence of the PCI clock for PME# operation.
When this bit is clear, it indicates that no PCI clock is required for the function to generate PME#.
Functions that do not support PME# generation in any state must return 0 for this field.
Hardwired to 0 to indicate the device does not support PME# generation.

18:16

0x3

RO

(VERSION)

This device complies with revision 1.2 of the PCI Power Management Interface Specification.

15:8

0x0

RO

Next Capability Pointer (NEXT_​CAPABILITY_​POINTER)

This field is hardwired to 00h, indicating the end of the capabilities linked list.

7:0

0x1

RO

Capability ID (CAPABILITY_​ID)

01h indicates that this is a power management capability.