31:24

0x0

RO

(DATA)

The data register, data scale and data select registers are not supported. Hardwired to zero.

23:16

0h

RO

Reserved

15

0x0

RO

PME# Status (PME_​STATUS)

This bit is set when the function would normally assert the PME# signal independent of the state of the PME_​En bit.
This bit is hardwired to 0b to indicate that PME# assertion from D3 (cold) is not supported.

14:13

0x0

RO

Data Scale (DATA_​SCALE)

The data register, data scale and data select registers are not supported.

12:9

0x0

RO

Data Select (DATA_​SELECT)

The data register, data scale and data select registers are not supported.

8

0x0

RO

PME Enable (PME_​ENABLE)

This bit is hardwired to 0b to indicate that PME# assertion from D3 (cold) is disabled.

7:4

0h

RO

Reserved

3

0x1

RO

No Soft Reset (NO_​SOFT_​RESET)

When set to 1 this bit indicates that the device is transitioning from D3hot to D0 because the power state commands do not perform a internal reset. Config context is preserved. Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits. When clear the devices do not perform an internal reset upon transitioning from D3hot to D0 via software control of the power state bits. Regardless of this bit the devices that transition from a D3hot to D0 by a system or bus segment reset will return to the device state D0 uninitialized with only PME context preserved if PME is supported and enabled.

2

0h

RO

Reserved

1:0

0x0

RW

Power State (POWER_​STATE)

This field indicates the current power state of the device and can be used to set the device into a new power state.
If software attempts to write an unsupported state to this field, the write operation must complete normally on the bus, but the data is discarded and no state change occurs.