12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
PRE Command Timing (TC_PRE_0_0_0_MCHBAR) – Offset E000
DDR timing constraints related to PRE commands
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
63 | 0h | RO | Reserved |
62:59 | 0x2 | RW | Derating Extensions (derating_ext) Holds LPDDR timing parameters derating tRAS, tRRD, tRP and tRCD in tCK (WCK for LPDDR5) cycles. |
58:51 | 0x8 | RW | tRCD Timing Parameter (tRCD) Holds DDR timing parameter tRCD |
50:42 | 0x1C | RW | tRAS Timing Parameter (tRAS) Holds DDR timing parameter tRAS. |
41:32 | 0x18 | RW | tWRPRE Timing Parameter (tWRPRE) Holds DDR timing parameter tWRPRE. |
31:24 | 0h | RO | Reserved |
23:20 | 0x4 | RW | tPPD Timing Parameter (tPPD) Holds DDR timing parameter tPPD. |
19:13 | 0x6 | RW | tRDPRE Timing Parameter (tRDPRE) Holds DDR timing parameter tRDPRE. |
12:8 | 0x0 | RW | tRPab_ext Timing Parameter (tRPab_ext) Holds the value of tRPab-tRPpb for LPDDR in tCK (WCK for LPDDR5) cycles. |
7:0 | 0x8 | RW | tRP Timing Parameter (tRP) Holds DDR timing parameter tRP (and tRCD). |