31:24

0x23

RW

tREFI x9 (tREFIx9)

Maximum time allowed between refreshes to a rank (in intervals of 1024 DCLK cycles).
Should be programmed to 8 * tREFI / 1024 (to allow for possible delays from ZQ or ISOC).

23:20

0x5

RW

Raise Block Wait (RAISE_​BLK_​WAIT)

Number of clocks the Main refresh FSM blocks the rank and waits before it progresses to any mantainance operations.
Notes this register defined to allow enough time for MC safe logic to indicate to all downstream agents whether it is safe to issue MNT operations. the pipeline latency is 5 clocks in all cases except for LP5 Gear1 where it can be 7 clocks due to longer autosync read/wriite commands.
So this register is specified in MC DCLKs and hardware will not change it based on gear.

19:18

0x1

RW

Self Refresh Exit - Refresh Debits (SRX_​Ref_​Debits)

Number of Refresh debits to be given on Self refresh exit.
Set 1 for LPDDR4/DDR4 and 2 for LPDDR5/DDR5.

17

0x1

RW

High Priority Referesh on MRS (HPRefOnMRS)

Setting this bit will enable MRS refresh at the beginning of MRS flow if the rank reached High Priority refresh WM.
Should be set by default, it's intended for System Agent SpeedStep as MC can enter Self refresh while owing refreshes.

16

0x0

RW

Enable tREFI Counter While MC Refresh Enable is not Set (CounttREFIWhileRefEnOff)

Setting this bit will enable tREFI counter while MC refresh enable is not set.
Sometimes refresh enable bit is cleared in order to block maintenance operetions.
This bit will keep tREFI counter on, but won't increase refresh debt, as the MC reset debt when refresh_​enable bit not set.

15:12

0x9

RW

Refresh Panic Threshold (Refresh_​panic_​wm)

tREFI count level in which the refresh priority is panic (default is 9).
The Maximum value for this field is 9.

11:8

0x8

RW

Refresh Priority Threshold (Refresh_​HP_​WM)

tREFI count level that turns the refresh priority to high (default is 8)

7:0

0xF

RW

Rank Idle (OREF_​RI)

Rank idle period that defines an opportunity for refresh, in DCLK cycles