Remap Base (REMAPBASE_0_0_0_MCHBAR) – Offset D890 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Remap Base (REMAPBASE_0_0_0_MCHBAR) – Offset D890

The value in this register defines the lower boundary of the Remap window.
The Remap window is inclusive of this address.
In the decoder A[19:0] of the Remap Base Address are assumed to be 0's.
Thus the bottom of the defined memory range will be aligned to a 1MB boundary.
When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled.
These bits are Intel TXT lockable.

Bit Range	Default	Access	Field Name and Description
63:39	0h	RO	Reserved
38:20	0x7FFFF	RW	Remap Base Address (REMAPBASE) The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder Address[19:0] of the Remap Base Address are assumed to be 0's. Thus the bottom of the defined memory range will be aligned to a 1MB boundary. When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. These bits are Intel TXT lockable.
19:0	0h	RO	Reserved

Bit Range

Default

Access

Field Name and Description

63:39

Reserved

38:20

0x7FFFF

Remap Base Address (REMAPBASE)

The value in this register defines the lower boundary of the Remap window.
The Remap window is inclusive of this address.
In the decoder Address[19:0] of the Remap Base Address are assumed to be 0's.
Thus the bottom of the defined memory range will be aligned to a 1MB boundary.
When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled.
These bits are Intel TXT lockable.

19:0

Reserved

Remap Limit (REMAPLIMIT_0_0_0_MCHBAR)

Address Compare for ECC Error Inject (ECC_Inj_Addr_Compare_0_0_0_MCHBAR) Remap Limit (REMAPLIMIT_0_0_0_MCHBAR)