15:5

0h

RO

Reserved

4

0x0

RW

CRS Software Visibility Enable (CRSSVE)

This bit, when set, enables the Root Port to return Configuration Retry Status (CRS) Completion status to software.
1: Enable software to received a CRS status. This allows software to make the decision to re-issue the configuration request or move on and re-issue the request at a later time.
0: Disable software from receiving a CRS response. The PCIe will wait and re-issue the configuration request until it receives a response other than CRS without notifying software.

3

0x0

RW

PME Interrupt Enable (PIE)

When set, enables interrupt generation when RSTS.PS is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.PS already set).

2

0x0

RW

System Error on Fatal Error Enable (SFE)

When set, an SERR# will be generated if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. This register is not dependent on CMD.SEE being set.

1

0x0

RW

System Error on Non-Fatal Error Enable (SNE)

When set, an SERR# will be generated if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. This register is not dependent on CMD.SEE being set.

0

0x0

RW

System Error on Correctable Error Enable (SCE)

When set, an SERR# will be generated if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. This register is not dependent on CMD.SEE being set.