31:28

0x0

RW

Write Rank 3 (Write_​Rank_​3)

Indicate which ranks should terminate when writing to rank 3 (bits 3:0 correspond to ODT pins 3:0.)
Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)

27:24

0x0

RW

Write Rank 2 (Write_​Rank_​2)

Indicate which ranks should terminate when writing to rank 2 (bits 3:0 correspond to ODT pins 3:0).
Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)

23:20

0x0

RW

Write Rank 1 (Write_​Rank_​1)

Indicate which ranks should terminate when writing to rank 1 (bits 3:0 correspond to ODT pins 3:0).
Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)

19:16

0x0

RW

Write Rank 0 (Write_​Rank_​0)

Indicate which ranks should terminate when writing to rank 0 (bits 3:0 correspond to ODT pins 3:0),
Note: In DDR5 this register should only be used for non target ODT

15:12

0x0

RW

Read Rank 3 (Read_​Rank_​3)

Indicate which ranks should terminate when reading from rank 3 (bits 3:0 correspond to ODT pins 3:0)
Note that according to DRAM spec the target rank should not be terminated.

11:8

0x0

RW

Read Rank 2 (Read_​Rank_​2)

Indicate which ranks should terminate when reading from rank 2 (bits 3:0 correspond to ODT pins 3:0)
Note that according to DRAM spec the target rank should not be terminated.

7:4

0x0

RW

Read Rank 1 (Read_​Rank_​1)

Indicate which ranks should terminate when reading from rank 1 (bits 3:0 correspond to ODT pins 3:0)
Note that according to DRAM spec the target rank should not be terminated.

3:0

0x0

RW

Read Rank 0 (Read_​Rank_​0)

Indicate which ranks should terminate when reading from rank 0 (bits 3:0 correspond to ODT pins 3:0)
Note that according to DRAM spec the target rank should not be terminated.