15:12

0h

RO

Reserved

11

0x0

RW

MC1 DDR5 CRC Error (MC1_​DDR5_​CRC)

This bit is deprecated.
Please refer to doc #655741 for details.

10

0x0

RW

MC0 DDR5 CRC Error (MC0_​DDR5_​CRC)

This bit is deprecated.
Please refer to doc #655741 for details.

9

0x0

RW

SCI on Multiple Bit Error (MC1_​DMESCI)

This bit is deprecated.
Please refer to doc #655741 for details.

8

0x0

RW

SCI on Single Bit Error (MC1_​DSESCI)

This bit is deprecated.
Please refer to doc #655741 for details.

7

0x0

RO

IBECC Uncorrectable Error (IBECC_​UC)

This bit is deprecated and kept for backwards compatibility.
IBECC error messages are logged in the MCA bank.

6

0x0

RO

IBECC Correctable Error (IBECC_​COR)

This bit is deprecated and kept for backwards compatibility.
IBECC error messages are logged in the MCA bank.

5

0x0

RW

SMI on FMHC Unsupported Request Event (FMUR)

SCI on FMHC unsupported request event
1: The Host Bridge generates an SCI special cycle over DMI when FMHC reports an unsupported request event.
0: Reporting of this condition via SCI messaging is disabled.

4

0x0

RW

SCI on FMHC CA event (FMCA)

SCI on FMHC CA event
1: The Host Bridge generates an SCI special cycle over DMI when FMHC reports a CA event.
0: Reporting of this condition via SCI messaging is disabled.

3

0x0

RW

SCI on FMI Asynchronous Notification (FMIAN)

SCI on FMI Asynchronous Notification error event
1: The Host Bridge generates an SCI special cycle over DMI when FMHC reports a Asynchronous Notification error event with Media dead or Health log critical notification.
0: Reporting of this condition via SCI messaging is disabled.

2

0x0

RW

SCI on FMHC thermal event (FMITHERMERR)

SCI on FMHC thermal event
1: The Host Bridge generates an SCI special cycle over DMI when FMHC reports a thermal event.
0: Reporting of this condition via SCI messaging is disabled.

1

0x0

RW

SCI on Multiple Bit Error (MC0_​DMESCI)

1: The Host generates an SCI DMI message when it detects a multiple-bit error reported by the DRAM controller.
0: Reporting of this condition via SCI messaging is disabled. For systems not supporting ECC this bit must be disabled.

0

0x0

RW

SCI on Single Bit Error (MC0_​DSESCI)

1: The Host generates an SCI DMI special cycle when the DRAM controller detects a single bit error.
0: Reporting of this condition via SCI messaging is disabled. For systems that do not support ECC this bit must be disabled.