15

0x0

RW/1C/V

Detected Parity Error (DPE)

Set when the port receives a poisoned TLP.

14

0x0

RW/1C/V

Received System Error (RSE)

Set when the port receives an ERR_​FATAL or ERR_​NONFATAL message from the device.

13

0x0

RW/1C/V

Received Master Abort (RMA)

Set when the port receives a completion with 'Unsupported Request' status from the device.

12

0x0

RW/1C/V

Received Target Abort (RTA)

Set when the port receives a completion with 'Completion Abort' status from the device.

11

0x0

RW/1C/V

Signaled Target Abort (STA)

Set when the port generates a completion with 'Completion Abort' status to the device.

10:9

0x0

RO/V

Secondary DEVSEL# Timing Status (SDTS)

Reserved per PCI-Express spec
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 01b when read, else this register returns a value of 00b.

8

0x0

RW/1C/V

Data Parity Error Detected (DPD)

Set when the BCTRL.PERE, and either of the following two conditions occurs:
Port receives completion marked poisoned.
Port poisons a write request to the secondary side.

7

0x0

RO/V

Secondary Fast Back to Back Capable (SFBC)

Reserved per PCI Express spec
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 1b when read, else this register returns a value of 0b.

6

0h

RO

Reserved

5

0x0

RO

Secondary 66 MHz Capable (SC66)

Reserved per PCI Express spec

4:0

0h

RO

Reserved