12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Slot Control (SLCTL) – Offset 58
Slot Control
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:14 | 0h | RO | Reserved |
13 | 0x0 | RW | Auto Slot Power Limit Disable (ASPLD) When set, this bit disables automatic sending of Set_Slot_Power_Limit message when the link transitions from non-DL_Up status to DL_Up status. |
12 | 0x0 | RW | Data Link Layer State Changed Enable (DLLSCE) When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field is changed. |
11 | 0x0 | RW | Electromechanical Interlock Control (EMIC) When software writes either a 1 to this bit, The PCIe port pulses the EMIL pin per PCIExpress Server/Workstation Module Electromechanical Spec Rev 1.0. |
10 | 0x0 | RW | Power Controller Control (PCC) This bit indicates the current state of the Power applied to the slot of the PCI Express port. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. |
9:8 | 0x0 | RW | Power Indicator Control (PIC) If a Power Indicator is implemented, writes to this register set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. |
7:6 | 0x0 | RW | Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this register sets the Attention Indicator to the written state. Reads of this field reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. |
5 | 0x0 | RW | Hot Plug Interrupt Enable (HPE) When set, enables generation of a hot plug interrupt on enabled hot plug events. |
4 | 0x0 | RW | Command Completed Interrupt Enable (CCE) This field enables the generation of Hot-plug interrupts when a command is completed by the Hot-plug controller connected to the PCI-Express port. |
3 | 0x0 | RW | Presence Detect Changed Enable (PDE) When set, enables the generation of a hot plug interrupt or wake message when the presence detect logic changes state. |
2 | 0x0 | RW | MRL Sensor Changed Enable (MSE) This bit enables the generation of hot-plug interrupts or wake messages via a MRL Sensor changed event. |
1 | 0x0 | RW | Power Fault Detected Enable (PFE) This bit enables the generation of hot-plug interrupts or wake messages via a power fault event. |
0 | 0x0 | RW | Attention Button Pressed Enable (ABE) This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. |