System Agent Performance Status (SA_PERF_STATUS_0_0_0_MCHBAR_PCU) – Offset 5918 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

System Agent Performance Status (SA_PERF_STATUS_0_0_0_MCHBAR_PCU) – Offset 5918

Indicates current various System Agent PLL ratios.
Operating frequency needs to be calculated according to reference clock (BCLK).

Bit Range	Default	Access	Field Name and Description
63:56	0h	RO	Reserved
55:40	0x0	RO/V	System Agent Voltage (SA_VOLTAGE) This register holds the System Agent voltage. This voltage value is valid only if the System Agent VR is SVID based. The precision is U3.13 (1/8192V resolution).
39:32	0x20	RO/V	PSF0 PLL Ratio (PSF0_RATIO) Reports the PSF0 PLL ratio. The PSF0 frequency is: Ratio * 16.67MHz. The supported ratios are {32, 48, 64} = {533MHz, 800MHz, 1067MHz}.
31:24	0x0	RO/V	RING UCLK PLL Ratio (UCLK_RATIO) RING UCLK RATIO. Reference=100Mhz
23:18	0x0	RO/V	IPU PS Ratio (IPU_PS_RATIO) The frequency is 25MHz * Ratio.
17:12	0x0	RO/V	IPU IS Divisor (IPU_IS_DIVISOR) The frequency is 1600MHz/Divisor.
11	0x0	RO/V	On Package Interface (OPI) Link Speed (OPI_LINK_SPEED) 0: 2Gb/s 1: 4Gb/s
10	0x0	RO/V	DDR QCLK Reference (QCLK_REFERENCE) 0: 133.34Mhz. In frequency calculations use 400.0MHz/3.0. 1: 100.00Mhz
9:2	0x0	RO/V	DDR QCLK Ratio (QCLK_RATIO) Reference determined by the QCLK_REFERENCE field.
1:0	0x0	RO/V	Last Display Engine Workpoint Request Served (LAST_DE_WP_REQ_SERVED) Last display engine workpoint request served by the PCU

GT Performance Status (GT_PERF_STATUS_0_0_0_MCHBAR_PCU)

Ratio Sum of Active GT Slice (PKG_GT_C0_ANY_SLICE_RATIO_0_0_0_MCHBAR_PCU) GT Performance Status (GT_PERF_STATUS_0_0_0_MCHBAR_PCU)