31:16

0h

RO

Reserved

15

0x0

RW

Force Memory Master DLL When Display Engine is Active (MDLL_​ON_​DE)

Force memory master DLL on when the Display Engine is active.
This includes cases where memory is not accessed.
This bit has to be set only if there are issues with the memory DLL wakeup based on the Self Refresh exit indication from Display Engine.
0b: Display Engine wakes up memory DLL using the Self Refresh exit indication only
1b: Force Memory DLL on when the Display Engine is active

14

0x0

RW

Force Memory Controller PLL When Display Engine is Active (MPLL_​ON_​DE)

Force Memory PLLs (MCPLL and GDPLL) on when the Display Engine is active.
This includes cases where memory is not accessed.
This bit has to be set only if there are issues with the Memory PLL wakeup based on the Self Refresh exit indication from the Display Engine.
0b: Display Engine wakes up Memory PLLs using the Self Refresh exit indication only
1b: Force Memory PLLs on when the Display Engine is active

13

0x1

RW

System Agent Clock Gating Memory Controller PLL (SACG_​MPLL)

When this bit is set to 1b, FCLK will never be gated when the memory controller PLL is ON.
Otherwise, FCLK gating policies are not affected by the locking of the memory controller PLLs.

12

0x0

RW

Non-Snoop Wake Self Refresh Exit (NSWAKE_​SREXIT)

When this bit is set to 1b, a Non-Snoop wakeup signal from the PCH will cause the PCU to force the memory controller to exit from Self-Refresh.
Otherwise, the Non-Snoop indication will not affect the Self Refresh exit policy.

11

0x0

RW

System Agent Clock Gating Self Refresh Exit (SACG_​SREXIT)

The Display Engine can indicate to the PCU that it wants the Memory Controller to exit self-refresh.
When this bit is set to 1b, this request from the Display Engine will cause FCLK to be ungated.
Otherwise, this request from the Display Engine has no effect on FCLK gating.

10

0x0

RW

Master DLL Shutdown Power State Enable (MDLL_​OFF_​SEN)

This bit indicates when the Memory Master DLL may be shutdown based on link active power states.
0b: Memory DLL may be shut down in L1 and deeper sleep states.
1b: Memory DLL may be shut down in L0s and deeper sleep states.

9

0x0

RW

Memory Controller PLL Shutdown Power State Enable (MPLL_​OFF_​SEN)

This bit indicates when the Memory PLLs (MCPLL and GDPLL) may be shutdown based on link active power states.
0b: Memory PLLs may be shut down in L1 and deeper sleep states.
1b: Memory PLLs may be shut down in L0s and deeper sleep states.

8

0x1

RW

System Agent Clock Gating Power State Enable (SACG_​SEN)

This bit indicates when the System Agent clock gating is possible based on link active power states.
0b: System Agent clock gating is allowed in L1 and deeper sleep states.
1b: System Agent clock gating is allowed in L0s and deeper sleep states.

7:3

0h

RO

Reserved

2

0x1

RW

PCIe PLL Shutdown Enable (PPLL_​OFF_​ENA)

This bit is used to enable shutting down the PCIe/DMI PLL.
0b: PLL shutdown is not allowed
1b: PLL shutdown is allowed

1

0x1

RW

Memory Controller PLL Shutdown Enable (MPLL_​OFF_​ENA)

This bit is used to enable shutting down the Memory Controller PLLs (MCPLL and GDPLL).
0b: PLL shutdown is not allowed
1b: PLL shutdown is allowed

0

0x0

RW

System Agent Clock Gating Enable (SACG_​ENA)

This bit is used to enable or disable the System Agent Clock Gating (FCLK).
0b: System Agent Clock Gating is Not Allowed
1b: System Agent Clock Gating is Allowed