31

0x0

RO/V

(VALID)

This bit indicates that the TEMPERATURE field is valid. It is set by PCODE if the temperature is within valid thermal sensor range.

30:27

0x1

RO

(RESOLUTION)

Supported resolution in degrees C.

26:24

0h

RO

Reserved

23:16

0x0

RO/V

(TEMPERATURE)

This is a temperature offset in degrees C below theTJ Max temperature. This number is meaningful only if VALID bit in this register is set.

15

0x0

RW/0C/V

Cross Domain limit log (CROSS_​DOMAIN_​LIMIT_​LOG)

R/WC0 - If set (1), indicates another hardware domain (e.g. processor graphics) has limited energy efficiency optimizations in the processor core domain since the last clearing of this bit or a reset. This bit is sticky, software may clear this bit by writing a zero (0).

14

0x0

RO/V

Cross Domain Limit status (CROSS_​DOMAIN_​LIMIT_​STATUS)

RO - If set (1), indicates another hardware domain (e.g. processor graphics) is currently limiting energy efficiency optimizations in the processor core domain.

13

0x0

RW/0C/V

Curent Limit log (CURRENT_​LIMIT_​LOG)

R/WC0 - If set (1), an electrical current limit has been exceeded that has adversely impacted energy efficiency optimizations since the last clearing of this bit or a reset. This bit is sticky, software may clear this bit by writing a zero (0).

12

0x0

RO/V

Current Limit status (CURRENT_​LIMIT_​STATUS)

RO - If set (1), indicates an electrical current limit (e.g. Electrical Design Point/IccMax) is being exceeded and is adversely impacting energy efficiency optimizations.

11

0x0

RW/0C/V

Power Limitation log (POWER_​LIMITATION_​LOG)

R/WC0 - Sticky bit which indicates whether the current P-state is limited by power limitation since the last clearing of this bit or a reset.
SW may clear this bit by writing a zero (0).
For legacy P state method, this bit will be set only if the P-state is limit below the guaranty level.

10

0x0

RO/V

Power Limitation status (POWER_​LIMITATION_​STATUS)

RO - Indicates whether the current P-state is limited by power limitation.
For legacy P state method, this bit will be set only if the P-state is limit below the guaranty level.

9

0x0

RW/0C/V

THRESHOLD2 log (THRESHOLD2_​LOG)

Sticky log bit that asserts on a 0 to 1 or a 1 to 0 transition of the THRESHOLD2_​STATUS bit.
This bit is set by HW and cleared by SW.

8

0x0

RO/V

THRESHOLD2 status (THRESHOLD2_​STATUS)

Indicates that the current temperature is higher than or equal to Threshold 2 temperature.

7

0x0

RW/0C/V

THRESHOLD1 log (THRESHOLD1_​LOG)

Sticky log bit that asserts on a 0 to 1 or a 1 to 0 transition of the THRESHOLD1_​STATUS bit.
This bit is set by HW and cleared by SW.

6

0x0

RO/V

THRESHOLD1 status (THRESHOLD1_​STATUS)

Indicates that the current temperature is higher than or equal to Threshold 1 temperature.

5

0x0

RW/0C/V

Outof Spec log (OUT_​OF_​SPEC_​LOG)

Sticky log bit indicating that the processor operating out of its thermal specification since the last time this bit was cleared.
This bit is set by HW on a 0 to 1 transition of OUT_​OF_​SPEC_​STATUS.

4

0x0

RO/V

Outof Spec status (OUT_​OF_​SPEC_​STATUS)

Status bit indicating that the processor is operating out of its thermal specification. Once set, this bit should only clear on a reset.

3

0x0

RW/0C/V

PROCHOT log (PROCHOT_​LOG)

Sticky log bit indicating that xxPROCHOT# has been asserted since the last time this bit was cleared by SW.
This bit is set by HW on a 0 to 1 transition of PROCHOT_​STATUS.

2

0x0

RO/V

PROCHOT status (PROCHOT_​STATUS)

Status bit indicating that xxPROCHOT# is currently being asserted.

1

0x0

RW/0C/V

Thermal Monitor log (THERMAL_​MONITOR_​LOG)

Sticky log bit indicating that the core has seen a thermal monitor event since the last time SW cleared this bit.
This bit is set by HW on a 0 to 1 transition of THERMAL_​MONITOR_​STATUS.

0

0x0

RO/V

Thermal Monitor Status (THERMAL_​MONITOR_​STATUS)

Status bit indicating that the Thermal Monitor has tripped and is currently thermally throttling.