12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
Virtual Channel 1 Resource Control (V1CTL) – Offset 2A0
Virtual Channel 1 Resource Control
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW/L | Virtual Channel Enable (EN) Enables the VC when set. Disables the VC when cleared. |
30:28 | 0h | RO | Reserved |
27:24 | 0x0 | RW/L | Virtual Channel Identifier (ID) Indicates the ID to use for this virtual channel |
23:20 | 0h | RO | Reserved |
19:17 | 0x0 | RW | Function Arbitration Select (FAS) This field configures the VC resource to provide a particular Function Arbitration service. |
16 | 0x0 | RW | Load Function Arbitration Table (LFAT) When Set, this bit updates the Function Arbitration logic from the Function Arbitration Table for the VC resource. This bit is only valid when the Function Arbitration Table is used by the selected Function Arbitration scheme (that is indicated by a Set bit in the Function Arbitration Capability field selected by Function Arbitration Select). |
15:10 | 0x0 | RW/L | Extended TC/VC Map (ETVM) Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic class bit. |
9:8 | 0h | RO | Reserved |
7:1 | 0x0 | RW | Transaction Class / Virtual Channel Map (TVM) This field indicates the TCs that are mapped to the VC resource. |
0 | 0h | RO | Reserved |