31

0x0

RO

Receiver Eye Margin Error Tracking Mechanism Disable (REMETMD)

When this bit is set MAC will not track Error count during Receiver Equalization (EQ Phase 2 - PDMI, EQ Phase 3 - PCIe). Preset/Coeff evaluation will be based on FOM returned by PHY alone.
This bit must be configured before training to GEN3 data rate.

30:9

0h

RO

Reserved

8

0x0

RW

Function Disable VNN Removal (FDVNNRE)

When assert, controller will assert vnnremoval_​en_​b to SOC when link is function disable, so that VNN is allow to be remove when platform permitted.

7

0x0

RW

Hot Plug VNN Removal Enable (HPVNNRE)

When assert, controller will assert vnnremoval_​en_​b to SOC when clkreq_​b deassetion in Detect state, so that VNN is allow to be remove when platform permitted.

6

0x0

RW

Detect Not PCIe VNN Removal Enable (DNPVNNRE)

When assert, controller will assert vnnremoval_​en_​b to SOC when link entering Detect Not PCIe when link is unown, so that VNN is allow to be remove when platform permitted.

5

0x0

RW

RTD3 VNN Removal Enable (RTD3VNNRE)

When assert, controller will assert vnnremoval_​en_​b to SOC when link entering L23 due to RTD3, so that VNN is allow to be remove when platform permitted.

4

0x0

RW

Link Disable VNN Removal Enable (LDVNNRE)

When assert, controller will assert vnnremoval_​en_​b to SOC when link entering Link Disable, so that VNN is allow to be remove when platform permitted.

3:2

0x0

RW

Internal States Propagation Latency For VNN Removal Exit (ISPLFVNNRE)

This register configure internal delay of IP to allow boundary lock to deassert. This counter will start count after contexts propagation is done and early boundary lock is deassert.
00 8 osc clocks
01 16 osc clocks
10 32 osc clocks
11 64 osc clocks
Note: For each x4 instance, only the value from Port 1 is used.
This is a per controller register

1:0

0x1

RW

Link Reset Suppression Latency For VNN Removal Exit (LRSLFVNNRE)

This register configure the Link Reset Suppression latency after pmc had deassert restore_​b during VNN Removal, and link clock pll had achieved lock. Link reset will be suppress upon IP Inaccessible exit with restore_​b assertion, and the counter will start count when restore_​b deassert with link clock had achieved lock. After timer expire, link reset will be deassert.
00 4 osc clocks
01 8 osc clocks
10 16 osc clocks
11 32 osc clocks
Note: For each x4 instance, only the value from Port 1 is used.
This is a per controller register